1. Field of the Invention
The present invention relates to a binary operator, more particularly, to a carry select adder circuit (CSA: including a borrow select subtracter in a parallel full subtracter) and a block look ahead carry generator circuit (BLACG: including a block look ahead borrow generator circuit in a parallel full subtracter) in a parallel full adder.
2. Description of the Related Art
Recently, along with the increase in the amounts of data, a demand has arisen for higher speeds of data processing by operators. As one means for achieving high speed data processing, there is known the carry look ahead (CLA) method. This carry look ahead method attempts to achieve high speed in the speed of addition by looking ahead at the necessary carry operation for each digit in advance. However, according to this carry look ahead method, an increase in the data length is accompanied with an unlimited increase in the operation elements and so is not practical.
On the other hand, as a suitable method for when the data length is particularly long (for example, 32 bits, 64 bits), there is known the carry select adder (CSA) method. According to the carry select adder method, before the data is divided into a plurality of blocks and the real carry signal from the lower block is generated in the adders of the various blocks, a sum signal in the case of assumption of the carry being "0" and a sum signal in the case of assumption of the carry being "1" are respectively generated. At the point of time when the real carry signal coming up from the adder of the lower block is input, selection is made of the presumed sum signal (one of "0" or "1") corresponding to the logic of the real carry signal and that selected presumed sum signal is output as the real sum signal of the block adder.
In the prior art, a binary adder circuit using the block select look ahead system for cutting down on the number of elements of the circuit is shown in Japanese Unexamined Patent Publication (Kokai; JP, A) No. 60-105041. However, the adder circuit of JPA '041 is used for generating a real carry signal, and not generating a real sum signal. Further, the adder circuit does not generate directly by using a cumulative carry propagate signal and a cumulative carry generate signal, since the adder circuit does not comprise a cumulative carry propagate signal generating unit and a cumulative carry generate signal generating unit.